1. Field of the Invention
This invention relates to a liquid crystal display, and more particularly to a liquid crystal display panel and a fabricating method thereof.
2. Description of the Related Art
Generally, a liquid crystal display (LCD) controls light transmittance of a liquid crystal using an electric field to display a picture. The LCD drives the liquid crystal with an electric field that is formed between a pixel electrode and a common electrode arranged in opposition to each other on upper and lower substrates, respectively. The LCD includes a thin film transistor array substrate and a color filter array substrate that are joined in opposition to each other. A spacer for keeping constant a cell gap is positioned between the two array substrates. A liquid crystal fills the cell gap between the two array substrates.
The thin film transistor array substrate includes a plurality of signal wirings and thin film transistors. An alignment film is coated over the plurality of signal wirings and thin film transistors for aligning the liquid crystal. The color filter array substrate includes a color filter for implementing a color, a black matrix for preventing leakage of light, and an alignment film aligning the liquid crystal.
The thin film transistor array substrate has a complicated fabrication process. The large number of semiconductor processes as well as the need for many mask processes are major factors in the manufacturing cost of the liquid crystal display panel. To address these cost issues, fabrication techniques for a thin film transistor array substrate have been developed that reduce the number of mask processes. One mask process includes a lot of sub-processes, such as thin film deposition, cleaning, photolithography, etching, photo-resist stripping and inspection processes. Recently, a four-round mask process, which excludes one mask process from the pre-existent five-round mask process that was a standard mask process of the thin film transistor, has been developed.
FIG. 1 is a plan view illustrating a lower transistor array substrate adopting a related art four-round mask process, and FIG. 2 is a cross-sectional view of the thin film transistor array substrate taken along line II-II′ in FIG. 1. As shown in FIG. 1 and FIG. 2, a thin film transistor array substrate of a related art liquid crystal display panel includes a gate line 2 and a data line 4 provided on a lower substrate 1 in such a manner as to cross each other and to define a cell area, a gate insulating film 12 between the gate line 2 and the data line 4, a thin film transistor 30 provided adjacent to each crossing, a pixel electrode 22 provided in the cell area, a storage capacitor defined where the gate line 2 and a storage electrode 28 overlap, a gate pad 50 connected to the gate line 2, and a data pad 60 connected to the data line 4.
The thin film transistor 30 allows a pixel signal on the data line 4 to be applied to the pixel electrode 22 in response to a gate signal on the gate line 2. The thin film transistor 30 includes a gate electrode 6 connected to the gate line 2, a source electrode 8 connected to the data line 4, and a drain electrode 10 connected to the pixel electrode 22. Further, the thin film transistor 30 includes an active layer 14 overlapping the gate electrode 6 with a gate insulating film 12 between the active layer 14 and the gate electrode 6. A channel is defined between the source electrode 8 and the drain electrode 10 in the active layer 14.
The active layer 14 also overlaps the data line 4, a lower data pad electrode 62 and a storage electrode 28. An ohmic contact layer on the active layer 14 makes contact with the data line 4 and the source electrode 8. Another ohmic contact layer on the active layer 14 makes contact with the drain electrode 10. Other ohmic contact layers contact the lower data pad electrode 62 and the storage electrode 28, respectively.
The pixel electrode 22 is connected, via a first contact hole 20 passing through a protective film 18, to the drain electrode 10 of the thin film transistor 30, and is provided in a pixel area 5. An electric field can be formed between the pixel electrode 22 to which a pixel signal is supplied via the thin film transistor 30 and a common electrode (not shown) supplied with a reference voltage. Liquid crystal molecules between the thin film transistor array substrate and the color filter array substrate are rotated by the electric field due to a dielectric anisotropy. Transmittance of a light propagating through the pixel area 5 can be differentiated by the extent of the rotation of the liquid crystal molecules so as to implement a gray level scale.
The storage capacitor 40 includes the gate line 2 overlapped by the active layer 14, the ohmic contact layer 16, and a storage electrode 28. A gate insulating film 12 is positioned between the active layer 14 and the gate line 2. The storage electrode 28 is connected, via a second contact hole 42 through the protective film 18, to the pixel electrode 22. The storage capacitor 40 allows a pixel signal applied on the pixel electrode 22 to be stably maintained until the next pixel signal is applied.
The gate pad 50 is connected to a gate driver (not shown) for applying a gate signal to the gate line 2. The gate pad 50 includes a lower gate pad electrode 52 extending from the gate line 2 and an upper gate pad electrode 54 connected, via a third contact hole 56 through the gate insulating film 12 and the protective film 18, to the lower gate pad electrode 52. The data pad 60 is connected to a data driver (not shown) for applying a data signal to the data line 4. The data pad 60 includes a lower data pad electrode 62 extending from the data line 4, and an upper data pad electrode 64 connected, via a fourth contact hole 66 through the protective film 18, to an upper data pad electrode 64 connected to the lower data pad electrode 62.
A method of fabricating the thin film transistor array substrate of the liquid crystal display panel having the above-mentioned structure using the four-round mask process will be described in detail with reference to FIG. 3A to FIG. 3D, hereinafter.
Referring to FIG. 3A, a first conductive pattern group, including the gate line 2, the gate electrode 6 and the lower gate pad electrode 52, is provided on the lower substrate 1 by a first mask process. More specifically, a gate metal layer is formed on the lower substrate 1 by a deposition technique, such as sputtering. Then, the gate metal layer is patterned by a photolithography and an etching process using the first mask to form the first conductive pattern group, including the gate line 2, the gate electrode 6 and the lower gate pad electrode 52. The gate metal layer is made from an aluminum group metal, for example.
Referring to FIG. 3B, the gate insulating film 12 is coated onto the lower substrate 1 having the first conductive pattern group. Further, semiconductor patterns including the active layer 14 and the ohmic contact layer 16, and a second conductive pattern group, including the data line 4, the source electrode 8, the drain electrode 10, the lower data pad electrode and the storage electrode 28, are formed on the gate insulating film 12 by a second mask process. More specifically, the gate insulating film 12, an amorphous silicon layer, a n+ amorphous silicon layer and a data metal layer are sequentially provided on the lower substrate 1 having the first conductive pattern group by deposition techniques, such as plasma enhanced chemical vapor deposition (PECVD) or sputtering. The gate insulating film 12 is formed from an inorganic insulating material, such as silicon nitride (SiNx) or silicon oxide (SiOx). The data metal layer is selected from molybdenum (Mo), titanium (Ti), tantalum (Ta) or a molybdenum alloy, for example. Then, a photo-resist pattern is formed on the data metal layer by the photolithography using the second mask.
In this case, a diffractive exposure mask having a diffractive exposing part at a channel portion of the thin film transistor is used as a second mask. Thus, the channel portion of the photo-resist pattern has a lower height than other source/drain pattern portions. Subsequently, the data metal layer is patterned by a wet etching process using the photo-resist pattern to provide the second conductive pattern group, including the data line 4 with the source electrode 8 and drain electrode 10 integral to the data line 4 and the storage electrode 28.
Next, the n+ amorphous silicon layer and the amorphous silicon layer are patterned at the same time by a dry etching process using the same photo-resist pattern to thereby provide the ohmic contact layer 14 and the active layer 16. The photo-resist pattern having a relatively low height is removed from the channel portion by an ashing process and thereafter the data metal layer and the ohmic contact layer 16 of the channel portion are etched by the dry etching process. Then, the active layer 14 of the channel portion is exposed to disconnect the source electrode 8 from the drain electrode 10. The photo-resist pattern left on the second conductive pattern group is removed by a stripping process.
Referring to FIG. 3C, the protective film 18 including the first to fourth contact holes 20, 42, 56 and 66 is formed in the gate insulating film 12 having a second conductive pattern group. More specifically, the protective film 18 is formed entirely over the gate insulating film 12 having the data patterns deposited by a deposition technique, such as a plasma enhanced chemical vapor deposition (PECVD). Then, the protective film 18 is patterned by a photolithography and an etching process using a third mask to thereby define the first to fourth contact holes 20, 42, 56 and 66. The first contact hole 20 passes through the protective film 18 to expose the drain electrode 10. The second contact hole 42 passes through the protective film 18 to expose the storage electrode 28. The third contact hole 56 passes through both the protective film 18 and the gate insulating film 12 to expose the lower gate pad electrode 52. The fourth contact hole 66 passes through the protective film 18 to expose the lower data pad electrode 62.
When metal having a large dry etching ratio, such as molybdenum (Mo), is used as the data metal, the first, second and fourth contact holes 20, 42 and 66 pass through the drain electrode 10, the storage electrode 28 and the lower data pad electrode 62, respectively, and expose side surfaces of the drain electrode 10, the storage electrode 28 and the lower data pad electrode 62, respectively. The protective film 18 is made from an inorganic insulating material identical to the gate insulating film 12, or an organic insulating material, such as an acrylic organic compound having a small dielectric constant, BCB (benzocyclobutene) or PFCB (perfluorocyclobutane).
Referring to FIG. 3D, a third conductive pattern group patterns, including the pixel electrode 22, the upper gate pad electrode 54 and the upper data pad electrode 64, are provided on the protective film 18 by a fourth mask process. More specifically, a transparent conductive film is coated onto the protective film 18 by a deposition technique, such as sputtering. Then, the transparent conductive film is patterned by a photolithography and an etching process using a fourth mask to provide the third conductive pattern group, including the pixel electrode 22, the upper gate pad electrode 54 and the upper data pad electrode 64. The pixel electrode 22 is electrically connected, via the first contact hole 20, to the drain electrode while also being electrically connected, via the second contact hole 42, to the storage electrode 28. The upper gate pad electrode 54 is electrically connected, via the third contact hole 56, to the lower gate pad electrode 52. The upper data pad electrode 64 is electrically connected, via the fourth contact hole 66, to the lower data pad electrode 62. The transparent conductive film is one of indium-tin-oxide (ITO), tin-oxide (TO), indium-tin-zinc-oxide (ITZO) and indium-zinc-oxide (IZO).
As described above, the related art thin film transistor array substrate and the fabricating method thereof uses the four-round mask process, thereby reducing the number of fabricating processes and hence reducing manufacturing cost proportional to the number of fabricating processes in comparison to using the five-round mask process. However, the four-round mask process still has a complicated fabricating process. More particularly, the diffractive exposure mask used in the four-round mask process is more complicated and more expensive than a photo mask that just has a shielding part and a transmitting part. Thus, there is still a need to simplify the fabricating process and to reduce manufacturing costs.